Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally built on the top surface of a bulk substrate. The substrate is doped to form impurity diffusion layers (i.e. source and drain regions). A conductive layer is situated between the source and drain regions; the conductive layer operates as a gate for the transistor. The gate controls current in a channel between the source and the drain regions.
In the fabrication process, a gate length below 100 nm often requires a super-shallow (&lt;20 nm) junction (i.e. junction between the source and the channel and the junction between the drain and the channel). With the source/drain junction depth reduced, the lateral dopant diffusion under the gate becomes smaller. As such, smaller gate-to-channel overlap capacitance is achieved for a fixed gate length, which is beneficial to fast transistor switching speed. Shallow source/drain junction can also effectively suppress the sub-surface punchthrough and reduce susceptibility to short-channel effects.
Conventional fabrication processes use a pre-amorphization implant, such as Si.sup.+ or Ge.sup.+, for the fabrication of an ultra-shallow source/drain junction. Providing the pre-amorphization implant before the regular dopant implant (to form source and drain regions) creates a shallow amorphous layer or region near the silicon surface. The pre-amorphization provides the advantages of (1) effectively preventing the channeling effect associated with ion implantation, (2) reducing the dopant activation temperature (the typical dopant species is activated in amorphous silicon at a temperature &gt;550.degree. C.), and (3) significantly reducing the dopant transient-enhanced-diffusion (TED) effect. Nevertheless, one major limitation of the conventional pre-amorphization implant method is that the ultra-shallow junction is limited by the thinness (or shallowness) of the amorphous layer.
Thus, there is a need for a method of forming a super-shallow amorphous layer in silicon during the fabrication process. Further, there is a need to reduce the quantity of implant needed for creating the amorphous layer. Even further, there is a need for fabricating a transistor with the advantages provided by a super-shallow junction.